A transistor may include borderless contacts to reduce the distance between devices. To prevent the unlanded contact etch step (which precedes the contact deposition step) from etching into an adjoining isolation structure, an etch stop layer may be formed on the surface of the device prior to performing that etch step. When the etch stop layer is blanket deposited over an entire CMOS device, it covers both the NMOS transistors and the PMOS transistors.
The etch stop layer may apply a tensile or compressive stress to each transistor's channel. That stress may enhance or degrade the transistor's performance, depending on the type of transistor. For example, when the etch stop layer is a silicon nitride layer that is in tension, it may enhance the performance of an NMOS transistor (e.g., by improving charge carrier mobility and velocity in the channel region, which increases the transistor's drive current), but degrade the performance of a PMOS transistor. Conversely, when the etch stop layer is in compression, it may enhance the performance of a PMOS transistor, but degrade the performance of an NMOS transistor.
Accordingly, there is a need for an integrated circuit with an etch stop layer that enhances the performance of a transistor having one conductivity type without significantly degrading the performance of a transistor having the opposite conductivity type. The present invention provides such a device, and a method for making it.